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SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions.
TM
memory
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50225-2E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & FCRAM
CMOS
128M (x16) FLASH MEMORY & 32M (x16) Mobile FCRAMTM
MB84VP24491HK-70
s FEATURES
* Power Supply Voltage of 2.7 V to 3.1 V * High Performance 20 ns maximum page read access time, 70 ns maximum random access time (Flash) 20 ns maximum page read access time, 70 ns maximum random access time (FCRAM) * Operating Temperature -30 C to +85 C * Package 73-ball FBGA
(Continued)
s PRODUCT LINEUP
Flash Supply Voltage (V) Max Random Address Access Time (ns) Max Page Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) VCCf* = 3.0 V 70 20 70 20
+0.1V -0.3 V
FCRAM VCCr* = 3.0 V +0.1V -0.3 V 70 20 70 40
*: Both VCCf and VCCr must be the same level when either part is being accessed.
s PACKAGE
73-ball plastic FBGA
(BGA-73P-M03)
MB84VP24491HK-70
(Continued)
-- FLASH MEMORY * 0.13 m Process Technology * Dual Chip Enable (CE0f, CE1f) CE0f controls 64M bits (Bank A and Bank B) region and CE1f controls 64M bits (Bank C and Bank D) bits region. * Single 3.0 V Read, Program and Ease Minimized system level power requirements * Simultaneous Read/Write Operations (Dual Bank) * FlexBankTM *1 Bank A(CE0f): 16 Mbit (4 KW x8 and 32 KW x31) Bank B(CE0f): 48 Mbit (32 KW x96) Bank C(CE1f): 48 Mbit (32 KW x96) Bank D(CE1f): 16 Mbit (4 KW x8 and 32 KW x31) * High Performance Page Mode 20 ns maximum page access time (70 ns random access time) * 8 words Page Access Capability * Minimum 100,000 Program/Erase Cycles * Sector Erase Architecture Eight 4 Kwords, two hundred fifty-four 32 Kwords, eight 8 Kwords sectors. Any combination of sectors can be concurrently erased. Also supports full chip erase * Dual Boot Block Sixteen 4Kwords boot block sectors, eight at the top of the address range and eight at the bottom of the address range * HiddenROM Region 256 byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC Input Pin At VIL, allows protection of "outermost" 2x4 K words on both ends of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance * Embedded EraseTM *2 Algorithms Automatically preprograms and erases the chip or any sector * Embedded ProgramTM *2 Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion * Ready/Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic Sleep Mode When addresses remain stable, the device automatically switches itself to low power mode * Low VCC Write Inhibit 2.5 V * Program Suspend/Resume Suspends the program operation to allow a read in another byte * Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device * Hardware Reset Pin (RESET) Hardware method to reset the device for reading array data (Continued)
2
MB84VP24491HK-70
(Continued) * New Sector Protection Persistent Sector Protection Password Sector Protection * Please refer to "MBM29RM12DH" Datasheet in detailed function
-- FCRAMTM *3 * Power Dissipation Operating : 30 mA Max Standby : 100 A Max * Power Down Mode Sleep : 10 A Max 4M Partial : 45 A Max 8M Partial : 55 A Max 16M Partial: 70 A Max * Power Down Control by CE2r * Byte Write Control: LB(DQ7 to DQ0), UB(DQ15 to DQ8) * 8 words Page Access Capability
*1: FlexBankTM is a trademark of Fujitsu Limited, Japan. *2: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. *3: Mobile FCRAMTM is a trademark of Fujitsu Limited, Japan.
3
MB84VP24491HK-70
s PIN ASSIGNMENT
(Top View) Marking Side
A10 N.C.
B10 N.C. D9 A15 C8 A11 C7 A8 B6 N.C. B5 N.C. C6 WE C5 WP/ACC C4 LB C3 A7 D8 A12 D7 A19 D6 CE2r D5 RESET D4 UB D3 A6 D2 A3 E9 A21 E8 A13 E7 A9 E6 A20 E5 RY/BY E4 A18 E3 A5 E2 A2
F10 N.C. F9 CE1f F8 A14 F7 A10
G10 N.C. G9 A16 G8 N.C. G7 DQ6 H9 N. C. H8 DQ15 H7 DQ13 H6 DQ4 H5 DQ3 J9 VSS J8 DQ7 J7 DQ12 J6 VCCr J5 VCCf J4 DQ10 J3 DQ0 J2 CE1r K8 DQ14 K7 DQ5 K6 N.C. K5 DQ11 K4 DQ2 K3 DQ8
L10 N.C.
M10 N.C.
L6 N.C. L5 N.C.
F4 A17 F3 A4 F2 A1 F1 N.C.
G4 DQ1 G3 VSS G2 A0 G1 N.C.
H4 DQ9 H3 OE H2 CE0f
A1 N.C.
B1 N.C.
C1 N.C.
L1 N.C.
M1 N.C.
(BGA-73P-M03)
4
MB84VP24491HK-70
s PIN DESCRIPTION
Pin name A20 to A0 A21 DQ15 to DQ0 CE0f CE1f CE1r CE2r OE WE RY/BY UB LB RESET WP/ACC N.C. VSS VCCf VCCr Input/ Output I I I/O I I I I I I O I I I I -- Power Power Power Address Inputs (Common) Address Input (Flash) Data Inputs/Outputs (Common) Chip Enable (Flash) Chip Enable (Flash) Chip Enable (FCRAM) Chip Enable (FCRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Output (Flash) Open Drain Output Upper Byte Control (FCRAM) Lower Byte Control (FCRAM) Hardware Reset Pin/Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (FCRAM) Description
5
MB84VP24491HK-70
s BLOCK DIAGRAM
VCCf A21 to A0 A21 to A0 WP/ACC RESET CE0f CE1f 128 M bit Flash Memory (Dual CE) VSS RY/BY
DQ15 to DQ0
DQ15 to DQ0 VCCr A20 to A0 DQ15 to DQ0 VSS
LB UB WE OE CE1r CE2r
32 M bit FCRAM
6
MB84VP24491HK-70
s DEVICE BUS OPERATIONS
Operation*1, *2 Full Standby CE0f CE1f CE1r CE2r OE WE LB H H Output Disable*
3
UB X
A21 to A0 X X*
8
DQ7 to DQ0 High-Z
WP/ DQ15 to RESET ACC DQ8 *9 High-Z H X
H H H L H L H L
H L H H H H H
H
X
X
X
L H
H
H
H
X
X
X
High-Z
High-Z
H
X
Read from Flash*4
L H L H
H H H
L H H
H L L
X X X L
X X X L L H H L L H H X X X X
Valid Valid Valid
DOUT DIN DIN DIN
DOUT DIN DIN DIN DIN High-Z High-Z DIN DIN High-Z High-Z X High-Z X X
H H H
X X X
Write to Flash
Read from FCRAM
H
H
L
H
L
H
H L
Valid
High-Z DIN
H
X
FCRAM No Read
H
H
L
H
L
H
H L
Valid
High-Z DIN
H
X
Write to FCRAM
H
H
L
H
H*
7
L
H L
Valid
High-Z DIN
H
X
FCRAM No Write Flash Temporary Sector Group Unprotection*5 Flash Hardware Reset Flash Boot Block Sector Write Protection FCRAM Power Down*6
H X X X X
H X X X X
L X H X X
H X H X L
H* X X X X
7
L X X X X
H X X X X
Valid X X X X
High-Z X High-Z X X
H VID L X X
X X X L X
Legend: L = VIL, H = VIH, X can be either VIL or VIH, High-Z = High Impedance. See sDC CHARACTERISTICS for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : Do not apply for two or more states of the following conditions at the same time; * CE0f = VIL * CE1f = VIL * CE1r = VIL and CE2r = VIH *3 : Should not be kept FCRAM Output Disable condition longer than 1s. *4 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *5 : It is also used for the extended sector group protections. *6 : FCRAM Power Down mode can be entered from Standby state and all DQ pins are in High-Z state. Data retention depends on the selection of Power Down Program. Please refer to "Power Down Program" in FCRAM Characteristics part. *7 : OE can be VIL during Write operation if the following conditions are satisfied; 1) Write pulse is initiated by CE1r (refer to CE1r Controlled Write timing), or cycle time of the previous operation cycle is satisfied. 2) OE stays VIL during Write cycle. *8 : Can be either VIL or VIH but must be valid before Read or Write. *9 : Protect "outer most" 2x8K bytes (4 words) on both ends of the boot block sectors. 7
MB84VP24491HK-70
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET, WP/ACC *1 VCCf/VCCr Supply *1 RESET *2 WP/ACC *3 Symbol Tstg TA VIN, VOUT VCCf, VCCr VIN VIN Rating Min -55 -30 -0.3 -0.3 -0.5 -0.5 Max +125 +85 VCCf +0.3 VCCr +0.3 +3.3 + 13.0 +10.5 Unit C C V V V V V
*1 Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -1.0 V for periods of up to 5 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCr + 0.3V. During voltage transitions, input or I/O pins may overshoot to VCCf + 2.0 V or VCCr + 1.0 V for periods of up to 5 ns. *2: Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN - VCCf) does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3: Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCCf/VCCr Supply Voltages Symbol TA VCCf, VCCr Value Min -30 +2.7 Max +85 +3.1 Unit C V
Note: Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
8
MB84VP24491HK-70
s DC CHARACTERISTICS
Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current (Flash) WP/ACC Acceleration Program Current (Flash) Flash VCC Active Current (Read) *1 Flash VCC Active Current *2 Flash VCC Current (Standby) Flash VCC Current (Standby, Reset) Flash VCC Current (Automatic Sleep Mode) *3 Flash VCC Active Current (Read-while-Program) *5 Flash VCC Active Current (Read-while-Erase) *5 Flash VCC Active Current (Erase Suspend Program) Flash VCC Active Current (Page Mode Read) FCRAM VCC Active Current *8 FCRAM VCC Page Read Current *8 FCRAM VCC Standby Current *8 Symbol ILI ILO ILIT ILIA Conditions VIN = VSS to VCCf, VCCr VOUT = VSS to VCCf, VCCr, Output Disable VCCf = VCCf Max, RESET = 12.5 V VCCf = VCCf Max, WP/ACC = VACC Max CE (CE0f or CE1f) = VIL, OE= VIH CE (CE0f or CE1f) = VIL, OE= VIH f = 10 MHz f = 5 MHz Value Min -1.0 -1.0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- Max +1.0 +1.0 35 20 45 25 25 5 5 5 45 45 25 10 30 3 10 100 10 45 55 70 mA Unit A A A mA mA mA mA A A A mA mA mA mA
ICC1f
ICC2f ISB1f ISB2f ISB3f ICC3f ICC4f ICC5f ICC6f ICC1r ICC2r ICC3r ISB1r IDDPSr
CE (CE0f or CE1f) = VIL, OEf= VIH VCCf = VCCf Max,CE0f, CE1f = VCCf 0.3 V RESET= VCCf 0.3 V, WP/ACC =VCCf 0.3 V VCCf = VCCf Max, RESET= VSS 0.3 V VCCf = VCCf Max, CE0f, CE1f= VSS 0.3 V, RESET= VCCf 0.3 V, VIN = VCCf 0.3 V or VSSf0.3 V CE (CE0f or CE1f) = VIL, OE= VIH CE (CE0f or CE1f) = VIL, OE= VIH CE (CE0f or CE1f) = VIL, OE= VIH CE (CE0f or CE1f) = VIL, OE = VIH, 8 Word Read VCCr = VCCr Max, tRC / tWC =Min CE1r = VIL, CE2r = VIH, VIN = VIH or VIL, IOUT = 0mA*7 tRC / tWC =1 s VCCr = VCCr Max, VIN = VIH or VIL, CE1r = VIL, CE2r = VIH, IOUT = 0 mA *7, tPRC=Min VCCr = VCCr Max, VIN < 0.2V or > VCCr - 0.2V CE1r > VCCr - 0.2V, CE2r > VCCr- 0.2V Sleep 4M Partial 8M Partial 16M Partial
mA A A A A A
FCRAM VCC Power Down Current *8
IDDP4r VCCr = VCCr Max, CE2r < 0.2V, IDDP8r VIN = VIH or VIL IDDP16r
(Continued)
9
MB84VP24491HK-70
(Continued)
Parameter Input Low Level Input High Level Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) *4 Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration *4 Symbol VIL VIH VID Conditions -- -- -- Value Min -0.3 VCC x 0.8 11.5 Typ -- -- 12 Max VCC x 0.2 *6 VCC+ 0.2 * 12.5
6
Unit V V V
VACC
-- VCCf = VCCf Min, IOL = 0.1 mA VCCr = VCCr Min, IOL = 1.0 mA VCCf = VCCf Min, IOH = -0.1 mA VCCr = VCCr Min, IOH = -0.5 mA --
8.5
9.0
9.5 VCCf x 0.15 0.4 -- -- 2.5
V
VOLf Output Low Voltage Level VOLr VOHf Output High Voltage Level VOHr Flash Low VCCf Lock-Out Voltage VLKO
Flash FCRAM Flash FCRAM
-- -- VCCf x 0.85 2.4 2.3
-- -- -- -- 2.4
V V V V V
*1: The ICC current listed includes both the DC operating current and the frequency dependent component. *2: ICC active while Embedded Algorithm (program or erase) is in progress. *3: Automatic sleep mode enables the low power mode when address remains stable for 150 ns. *4: Applicable for only VCCf applying. *5: Embedded Algorithm (program or erase) is in progress. (@5 MHz) *6: VCC indicates lower of VCCf or VCCr. *7: FCRAM Characteristics are measured after following POWER-UP timing. *8: IOUT depends on the output load conditions.
10
MB84VP24491HK-70
s AC CHARACTERISTICS
* CE Timing Parameter CE Recover Time CE Hold Time CE1r High to WE Invalid time for Standby Entry Symbol JEDEC -- -- -- Standard tCCR tCHOLD tCHWX Condition -- -- -- Value Min 0 3 10 Max -- -- -- Unit ns ns ns
* Timing Diagram for alternating RAM to Flash
CE0f or CE1f
tCCR
tCCR
CE1r
WE
tCHWX tCHOLD
tCCR
tCCR
CE2r
* Flash Characteristics Please refer to "s128 M PAEG FLASH MEMORY CHARACTERISTICS for MCP". * FCRAM Characteristics Please refer to "s32 M FCRAM CHARACTERISTICS for MCP".
11
MB84VP24491HK-70
s 128 M PAGE FLASH MEMORY CHARACTERISTICS for MCP
1. Flexible Sector-erase Architecture on FLASH MEMORY (128M Page Flash)
* Sixteen 4K words, and two hundred fifty-four 32K words. * Individual-sector, multiple-sector, or bulk-erase capability.
CE0f
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 : 8KB : 8KB : 8KB : 8KB : 8KB : 8KB : 8KB : 8KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB : 64KB 000000h 001000h 002000h 003000h 004000h 005000h 006000h 007000h 008000h 010000h 018000h 020000h 028000h 030000h 038000h 040000h 048000h 050000h 058000h 060000h 068000h 070000h 078000h 080000h 088000h 090000h 098000h 0A0000h 0A8000h 0B0000h 0B8000h 0C0000h 0C8000h 0D0000h 0D8000h 0E0000h 0E8000h 0F0000h 0F8000h 100000h 108000h 110000h 118000h 120000h 128000h 130000h 138000h 140000h 148000h 150000h 158000h 160000h 168000h 170000h 178000h 180000h 188000h 190000h 198000h 1A0000h 1A8000h 1B0000h 1B8000h 1C0000h 1C8000h 1D0000h 1D8000h 1E0000h 1E8000h 1F0000h 1F8000h 1FFFFFh SA71 : 64KB SA72 : 64KB SA73 : 64KB SA74 : 64KB SA75 : 64KB SA76 : 64KB SA77 : 64KB SA78 : 64KB SA79 : 64KB SA80 : 64KB SA81 : 64KB SA82 : 64KB SA83 : 64KB SA84 : 64KB SA85 : 64KB SA86 : 64KB SA87 : 64KB SA88 : 64KB SA89 : 64KB SA90 : 64KB SA91 : 64KB SA92 : 64KB SA93 : 64KB SA94 : 64KB SA95 : 64KB SA96 : 64KB SA97 : 64KB SA98 : 64KB SA99 : 64KB SA100: 64KB SA101: 64KB SA102: 64KB SA103: 64KB SA104: 64KB SA105: 64KB SA106: 64KB SA107: 64KB SA108: 64KB SA109: 64KB SA110: 64KB SA111: 64KB SA112: 64KB SA113: 64KB SA114: 64KB SA115: 64KB SA116: 64KB SA117: 64KB SA118: 64KB SA119: 64KB SA120: 64KB SA121: 64KB SA122: 64KB SA123: 64KB SA124: 64KB SA125: 64KB SA126: 64KB SA127: 64KB SA128: 64KB SA129: 64KB SA130: 64KB SA131: 64KB SA132: 64KB SA133: 64KB SA134: 64KB 200000h 208000h 210000h 218000h 220000h 228000h 230000h 238000h 240000h 248000h 250000h 258000h 260000h 268000h 270000h 278000h 280000h 288000h 290000h 298000h 2A0000h 2A8000h 2B0000h 2B8000h 2C0000h 2C8000h 2D0000h 2D8000h 2E0000h 2E8000h 2F0000h 2F8000h 300000h 308000h 310000h 318000h 320000h 328000h 330000h 338000h 340000h 348000h 350000h 358000h 360000h 368000h 370000h 378000h 380000h 388000h 390000h 398000h 3A0000h 3A8000h 3B0000h 3B8000h 3C0000h 3C8000h 3D0000h 3D8000h 3E0000h 3E8000h 3F0000h 3F8000h 3FFFFFh SA135: 64KB SA136: 64KB SA137: 64KB SA138: 64KB SA139: 64KB SA140: 64KB SA141: 64KB SA142: 64KB SA143: 64KB SA144: 64KB SA145: 64KB SA146: 64KB SA147: 64KB SA148: 64KB SA149: 64KB SA150: 64KB SA151: 64KB SA152: 64KB SA153: 64KB SA154: 64KB SA155: 64KB SA156: 64KB SA157: 64KB SA158: 64KB SA159: 64KB SA160: 64KB SA161: 64KB SA162: 64KB SA163: 64KB SA164: 64KB SA165: 64KB SA166: 64KB SA167: 64KB SA168: 64KB SA169: 64KB SA170: 64KB SA171: 64KB SA172: 64KB SA173: 64KB SA174: 64KB SA175: 64KB SA176: 64KB SA177: 64KB SA178: 64KB SA179: 64KB SA170: 64KB SA181: 64KB SA182: 64KB SA183: 64KB SA184: 64KB SA185: 64KB SA186: 64KB SA187: 64KB SA188: 64KB SA189: 64KB SA190: 64KB SA191: 64KB SA192: 64KB SA193: 64KB SA194: 64KB SA195: 64KB SA196: 64KB SA197: 64KB SA198: 64KB 400000h 408000h 410000h 418000h 420000h 428000h 430000h 438000h 440000h 448000h 450000h 458000h 460000h 468000h 470000h 478000h 480000h 488000h 490000h 498000h 4A0000h 4A8000h 4B0000h 4B8000h 4C0000h 4C8000h 4D0000h 4D8000h 4E0000h 4E8000h 4F0000h 4F8000h 500000h 508000h 510000h 518000h 520000h 528000h 530000h 538000h 540000h 548000h 550000h 558000h 560000h 568000h 570000h 578000h 580000h 588000h 590000h 598000h 5A0000h 5A8000h 5B0000h 5B8000h 5C0000h 5C8000h 5D0000h 5D8000h 5E0000h 5E8000h 5F0000h 5F8000h 5FFFFFh
CE1f
SA199: 64KB SA200: 64KB SA201: 64KB SA202: 64KB SA203: 64KB SA204: 64KB SA205: 64KB SA206: 64KB SA207: 64KB SA208: 64KB SA209: 64KB SA210: 64KB SA211: 64KB SA212: 64KB SA213: 64KB SA214: 64KB SA215: 64KB SA216: 64KB SA217: 64KB SA218: 64KB SA219: 64KB SA220: 64KB SA221: 64KB SA222: 64KB SA223: 64KB SA224: 64KB SA225: 64KB SA226: 64KB SA227: 64KB SA228: 64KB SA229: 64KB SA230: 64KB SA231: 64KB SA232: 64KB SA233: 64KB SA234: 64KB SA235: 64KB SA236: 64KB SA237: 64KB SA238: 64KB SA239: 64KB SA240: 64KB SA241: 64KB SA242: 64KB SA243: 64KB SA244: 64KB SA245: 64KB SA246: 64KB SA247: 64KB SA248: 64KB SA249: 64KB SA250: 64KB SA251: 64KB SA252: 64KB SA253: 64KB SA254: 64KB SA255: 64KB SA256: 64KB SA257: 64KB SA258: 64KB SA259: 64KB SA260: 64KB SA261: 64KB SA262: 8KB SA263: 8KB SA264: 8KB SA265: 8KB SA266: 8KB SA267: 8KB SA268: 8KB SA269: 8KB 600000h 608000h 610000h 618000h 620000h 628000h 630000h 638000h 640000h 648000h 650000h 658000h 660000h 668000h 670000h 678000h 680000h 688000h 690000h 698000h 6A0000h 6A8000h 6B0000h 6B8000h 6C0000h 6C8000h 6D0000h 6D8000h 6E0000h 6E8000h 6F0000h 6F8000h 700000h 708000h 710000h 718000h 720000h 728000h 730000h 738000h 740000h 748000h 750000h 758000h 760000h 768000h 770000h 778000h 780000h 788000h 790000h 798000h 7A0000h 7A8000h 7B0000h 7B8000h 7C0000h 7C8000h 7D0000h 7D8000h 7E0000h 7E8000h 7F0000h 7F8000h 7F9000h 7FA000h 7FB000h 7FC000h 7FD000h 7FE000h 7FF000h 7FFFFFh
BANK A
BANK C
BANK B
12
BANK B
BANK D
BANK C
MB84VP24491HK-70
* FlexBankTM Architecture (128M Page Flash) Bank Splits 1 2 3 4 Bank 1 Volume 16 Mbit 48 Mbit 48 Mbit 16 Mbit Combination Bank A Bank B Bank C Bank D Volume 112 Mbit 80 Mbit 80 Mbit 112 Mbit Bank 2 Combination Remainder (Bank B, C, D) Remainder (Bank A, C, D) Remainder (Bank A, B, D) Remainder (Bank A, B, C)
* Example of Virtual Banks Combination (128M Page Flash) Bank Splits Bank 1 Volume Combination Sector Size 8 x 4 Kword + 31 x 32 Kword 16 x 4 Kword + 62 x 32 Kword Volume Bank 2 Combination Bank B + Bank C + Bank D Bank B + Bank C Bank A + Bank C + Bank D Bank C + Bank D Sector Size 8 x 4 Kword + 223 x 32 Kword
1
16 Mbit
Bank A
112 Mbit
2
32 Mbit
Bank A + Bank D
96 Mbit
192 x 32 Kword
3
48 Mbit
Bank B
96 x 32 Kword
80 Mbit
16 x 4 Kword + 158 x 32 Kword 8 x 4 Kword + 127 x 32 Kword
4
64 Mbit
Bank A + Bank B
8 x 4 Kword + 127 x 32 Kword
64 Mbit
Note : When multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. For example, suppose that erasing is taking place at both Bank A and Bank B, neither Bank A nor Bank B is read out (they would output the sequence flag once they were selected.) Meanwhile the system would get to read from either Bank C or Bank D.
13
MB84VP24491HK-70
* Simultaneous Operation (Dual CE) (128M Page Flash) The device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank can be selected by bank address (A21, A20) with zero latency. The device consists of the following four banks : CE0f control: Bank A : 8 x 4 KW and 31 x 32 KW; Bank B : 96 x 32 KW CE1f control: Bank C : 96 x 32 KW; Bank D : 8 x 4 KW and 31 x 32 KW. The possible combinations for simultaneous operation is show as following table. ( (Refer to Figure 11 Bank-toBank Read/Write Timing Diagram.) * Simultaneous Operation for Dual CE (128M Page Flash) Bank 1 (CE0f) Status Bank 2 (CE0f) Status Bank 1 (CE1f) Status Case 16 Mbit 48 Mbit 48 Mbit 1 2 3 4 5 6 7 8 9 10 11 12 13 14* 15* 16* 17* 18* 19* 20* 21* 22* 23* Read mode Autoselect mode Read mode Read mode Read mode Program mode Read mode Read mode Read mode Erase Mode Read mode Read mode Read mode Multiple Erase Mode Multiple Erase Mode Multiple Erase Mode Read mode Read mode Read mode Multiple Erase Mode Multiple Erase Mode Multiple Erase Mode Read mode Read mode Read mode Autoselect mode Read mode Read mode Read mode Program mode Read mode Read mode Read mode Erase Mode Read mode Read mode Multiple Erase Mode Read mode Read mode Multiple Erase Mode Multiple Erase Mode Read mode Multiple Erase Mode Multiple Erase Mode Read mode Multiple Erase Mode Read mode Read mode Read mode Autoselect mode Read mode Read mode Read mode Program mode Read mode Read mode Read mode Erase Mode Read mode Read mode Multiple Erase Mode Read mode Multiple Erase Mode Read mode Multiple Erase Mode Multiple Erase Mode Read mode Multiple Erase Mode Multiple Erase Mode
Bank 2 (CE1f) Status 16 Mbit Read mode Read mode Read mode Read mode Autoselect mode Read mode Read mode Read mode Program mode Read mode Read mode Read mode Erase Mode Read mode Read mode Multiple Erase Mode Read mode Multiple Erase Mode Multiple Erase Mode Read mode Multiple Erase Mode Multiple Erase Mode Multiple Erase Mode
* : Multiple Erase Mode requires multiple sector erase sequence which is followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than "tTOW".
14
MB84VP24491HK-70
2. Flexible Sector-erase Architecture
* Sector Address Tables (Bank A) (128M Page Flash) Chip Enable Sector Address Bank Address A20 A19 A18 A17 A16 A15 A14 A13 A12 000000000 000000001 000000010 000000011 000000100 000000101 000000110 000000111 000001XXX 000010XXX 000011XXX 000100XXX 000101XXX 000110XXX 000111XXX 001000XXX 001001XXX 001010XXX 001011XXX 001100XXX 001101XXX 001110XXX 001111XXX 010000XXX 010001XXX 010010XXX 010011XXX 010100XXX 010101XXX 010110XXX 010111XXX 011000XXX 011001XXX 011010XXX 011011XXX 011100XXX 011101XXX 011110XXX 011111XXX Sector Size (Kword) 4 4 4 4 4 4 4 4 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 06FFFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh
Bank
Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Bank A
CE0f CE1f A21 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0
15
MB84VP24491HK-70
* Sector Address Tables (Bank B) (128M Page Flash) Sector Address Chip Bank Enable Bank Sector Address CE0f CE1f A21 A20 A19 A18 A17 A16 A15 SA39 0 1 0 100000 SA40 0 1 0 100001 SA41 0 1 0 100010 SA42 0 1 0 100011 SA43 0 1 0 100100 SA44 0 1 0 100101 SA45 0 1 0 100110 SA46 0 1 0 100111 SA47 0 1 0 101000 SA48 0 1 0 101001 SA49 0 1 0 101010 SA50 0 1 0 101011 SA51 0 1 0 101100 SA52 0 1 0 101101 SA53 0 1 0 101110 SA54 0 1 0 101111 SA55 0 1 0 110000 SA56 0 1 0 110001 SA57 0 1 0 110010 SA58 0 1 0 110011 Bank B SA59 0 1 0 110100 SA60 0 1 0 110101 SA61 0 1 0 110110 SA62 0 1 0 110111 SA63 0 1 0 111000 SA64 0 1 0 111001 SA65 0 1 0 111010 SA66 0 1 0 111011 SA67 0 1 0 111100 SA68 0 1 0 111101 SA69 0 1 0 111110 SA70 0 1 0 111111 SA71 0 1 1 000000 SA72 0 1 1 000001 SA73 0 1 1 000010 SA74 0 1 1 000011 SA75 0 1 1 000100 SA76 0 1 1 000101 SA77 0 1 1 000110
A14 A13 A12 XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
Sector Size (Kword) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
(x 16) Address Range 100000h to 107FFFh 108000h to 10FFFFh 110000h to 117FFFh 118000h to 11FFFFh 120000h to 127FFFh 128000h to 12FFFFh 130000h to 137FFFh 138000h to 13FFFFh 140000h to 147FFFh 148000h to 14FFFFh 150000h to 157FFFh 158000h to 15FFFFh 160000h to 167FFFh 168000h to 16FFFFh 170000h to 177FFFh 178000h to 17FFFFh 180000h to 187FFFh 188000h to 18FFFFh 190000h to 197FFFh 198000h to 19FFFFh 1A0000h to 1A7FFFh 1A8000h to 1AFFFFh 1B0000h to 1B7FFFh 1B8000h to 1BFFFFh 1C0000h to 1C7FFFh 1C8000h to 1CFFFFh 1D0000h to 1D7FFFh 1D8000h to 1DFFFFh 1E0000h to 1E7FFFh 1E8000h to 1EFFFFh 1F0000h to 1F7FFFh 1F8000h to 1FFFFFh 200000h to 207FFFh 208000h to 20FFFFh 210000h to 217FFFh 218000h to 21FFFFh 220000h to 227FFFh 228000h to 22FFFFh 230000h to 237FFFh (Continued)
16
MB84VP24491HK-70
Bank
Sector
Bank B
SA78 SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116
Bank Address CE0f CE1f A21 A20 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
Chip Enable
Sector Address Sector Size (Kword) A19 A18 A17 A16 A15 A14 A13 A12 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111XXX 00000XXX 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 238000h to 23FFFFh 240000h to 247FFFh 248000h to 24FFFFh 250000h to 257FFFh 258000h to 25FFFFh 260000h to 267FFFh 268000h to 26FFFFh 270000h to 277FFFh 278000h to 27FFFFh 280000h to 287FFFh 288000h to 28FFFFh 290000h to 297FFFh 298000h to 29FFFFh 2A0000h to 2A7FFFh 2A8000h to 2AFFFFh 2B0000h to 2B7FFFh 2B8000h to 2BFFFFh 2C0000h to 2C7FFFh 2C8000h to 2CFFFFh 2D0000h to 2D7FFFh 2D8000h to 2DFFFFh 2E0000h to 2E7FFFh 2E8000h to 2EFFFFh 2F0000h to 2F7FFFh 2F8000h to 2FFFFFh 300000h to 307FFFh 308000h to 30FFFFh 310000h to 317FFFh 318000h to 31FFFFh 320000h to 327FFFh 328000h to 32FFFFh 330000h to 337FFFh 338000h to 33FFFFh 340000h to 347FFFh 348000h to 34FFFFh 350000h to 357FFFh 358000h to 35FFFFh 360000h to 367FFFh 368000h to 36FFFFh (Continued)
17
MB84VP24491HK-70
(Continued)
Chip Enable Sector Address Bank Address A20 A19 A18 A17 A16 A15 A14 A13 A12 101110XXX 101111XXX 110000XXX 110001XXX 110010XXX 110011XXX 110100XXX 110101XXX 110110XXX 110111XXX 111000XXX 111001XXX 111010XXX 111011XXX 111100XXX 111101XXX 111110XXX 111111XXX Sector Size (Kword) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 370000h to 377FFFh 378000h to 37FFFFh 380000h to 387FFFh 388000h to 38FFFFh 390000h to 397FFFh 398000h to 39FFFFh 3A0000h to 3A7FFFh 3A8000h to 3AFFFFh 3B0000h to 3B7FFFh 3B8000h to 3BFFFFh 3C0000h to 3C7FFFh 3C8000h to 3CFFFFh 3D0000h to 3D7FFFh 3D8000h to 3DFFFFh 3E0000h to 3E7FFFh 3E8000h to 3EFFFFh 3F0000h to 3F7FFFh 3F8000h to 3FFFFFh
Bank
Sector
Bank B
SA117 SA118 SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134
CE0f CE1f A21 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
18
MB84VP24491HK-70
* Sector Address Tables (Bank C) (128M Page Flash) Chip Enable Sector Address Bank Address A20 A19 A18 A17 A16 A15 A14 A13 A12 000000XXX 000001XXX 000010XXX 000011XXX 000100XXX 000101XXX 000110XXX 000111XXX 001000XXX 001001XXX 001010XXX 001011XXX 001100XXX 001101XXX 001110XXX 001111XXX 010000XXX 010001XXX 010010XXX 010011XXX 010100XXX 010101XXX 010110XXX 010111XXX 011000XXX 011001XXX 011010XXX 011011XXX 011100XXX 011101XXX 011110XXX 011111XXX 100000XXX 100001XXX 100010XXX 100011XXX 100100XXX 100101XXX 100110XXX Sector Size (Kword) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 400000h to 407FFFh 408000h to 40FFFFh 410000h to 417FFFh 418000h to 41FFFFh 420000h to 427FFFh 428000h to 42FFFFh 430000h to 437FFFh 438000h to 43FFFFh 440000h to 447FFFh 448000h to 44FFFFh 450000h to 457FFFh 458000h to 45FFFFh 460000h to 467FFFh 468000h to 46FFFFh 470000h to 477FFFh 478000h to 47FFFFh 480000h to 487FFFh 488000h to 48FFFFh 490000h to 497FFFh 498000h to 49FFFFh 4A0000h to 4A7FFFh 4A8000h to 4AFFFFh 4B0000h to 4B7FFFh 4B8000h to 4BFFFFh 4C0000h to 4C7FFFh 4C8000h to 4CFFFFh 4D0000h to 4D7FFFh 4D8000h to 4DFFFFh 4E0000h to 4E7FFFh 4E8000h to 4EFFFFh 4F0000h to 4F7FFFh 4F8000h to 4FFFFFh 500000h to 507FFFh 508000h to 50FFFFh 510000h to 517FFFh 518000h to 51FFFFh 520000h to 527FFFh 528000h to 52FFFFh 530000h to 537FFFh (Continued)
Bank
Sector
Bank C
SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 SA146 SA147 SA148 SA149 SA150 SA151 SA152 SA153 SA154 SA155 SA156 SA157 SA158 SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173
CE0f CE1f A21 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0
19
MB84VP24491HK-70
Bank
Sector
Bank C
SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 SA186 SA187 SA188 SA189 SA190 SA191 SA192 SA193 SA194 SA195 SA196 SA197 SA198 SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212
Bank Address CE0f CE1f A21 A20 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Chip Enable
Sector Address Sector Size (Kword) A19 A18 A17 A16 A15 A14 A13 A12 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111XXX 00000XXX 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 538000h to 53FFFFh 540000h to 547FFFh 548000h to 54FFFFh 550000h to 557FFFh 558000h to 55FFFFh 560000h to 567FFFh 568000h to 56FFFFh 570000h to 577FFFh 578000h to 57FFFFh 580000h to 587FFFh 588000h to 58FFFFh 590000h to 597FFFh 598000h to 59FFFFh 5A0000h to 5A7FFFh 5A8000h to 5AFFFFh 5B0000h to 5B7FFFh 5B8000h to 5BFFFFh 5C0000h to 5C7FFFh 5C8000h to 5CFFFFh 6D0000h to 5D7FFFh 6D8000h to 5DFFFFh 5E0000h to 5E7FFFh 5E8000h to 5EFFFFh 5F0000h to 5F7FFFh 5F8000h to 5FFFFFh 600000h to 607FFFh 608000h to 60FFFFh 610000h to 617FFFh 618000h to 61FFFFh 620000h to 627FFFh 628000h to 62FFFFh 630000h to 637FFFh 638000h to 63FFFFh 640000h to 647FFFh 648000h to 64FFFFh 650000h to 657FFFh 658000h to 65FFFFh 660000h to 667FFFh 668000h to 66FFFFh
(Continued)
20
MB84VP24491HK-70
(Continued)
Chip Enable Sector Address Bank Address A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A19 A18 A17 A16 A15 A14 A13 A12 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111XXX Sector Size (Kword) 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 (x 16) Address Range 670000h to 677FFFh 678000h to 67FFFFh 680000h to 687FFFh 688000h to 68FFFFh 690000h to 697FFFh 698000h to 69FFFFh 6A0000h to 6A7FFFh 6A8000h to 6AFFFFh 6B0000h to 6B7FFFh 8B8000h to 6BFFFFh 6C0000h to 6C7FFFh 6C8000h to 6CFFFFh 6D0000h to 6D7FFFh 6D8000h to 6DFFFFh 6E0000h to 6E7FFFh 6E8000h to 6EFFFFh 6F0000h to 6F7FFFh 6F8000h to 6FFFFFh
Bank
Sector
Bank C
SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 SA226 SA227 SA228 SA229 SA230
CE0f CE1f A21 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1
21
MB84VP24491HK-70
* Sector Address Tables (Bank D) (128M Page Flash) Chip Enable Sector Address Sector Size (Kword) A19 A18 A17 A16 A15 A14 A13 A12 00000XXX 00001XXX 00010XXX 00011XXX 00100XXX 00101XXX 00110XXX 00111XXX 01000XXX 01001XXX 01010XXX 01011XXX 01100XXX 01101XXX 01110XXX 01111XXX 10000XXX 10001XXX 10010XXX 10011XXX 10100XXX 10101XXX 10110XXX 10111XXX 11000XXX 11001XXX 11010XXX 11011XXX 11100XXX 11101XXX 11110XXX 11111000 11111001 11111010 11111011 11111100 11111101 11111110 11111111 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 4 4 4 4 4 4 4 4 (x 16) Address Range 700000h to 707FFFh 708000h to 70FFFFh 710000h to 717FFFh 718000h to 71FFFFh 720000h to 727FFFh 728000h to 72FFFFh 730000h to 737FFFh 738000h to 73FFFFh 740000h to 747FFFh 748000h to 74FFFFh 750000h to 757FFFh 758000h to 75FFFFh 760000h to 767FFFh 768000h to 76FFFFh 770000h to 777FFFh 778000h to 77FFFFh 780000h to 787FFFh 788000h to 78FFFFh 790000h to 797FFFh 798000h to 79FFFFh 7A0000h to 7A7FFFh 7A8000h to 7AFFFFh 7B0000h to 7B7FFFh 7B8000h to 7BFFFFh 7C0000h to 7C7FFFh 7C8000h to 7CFFFFh 7D0000h to 7D7FFFh 7D8000h to 7DFFFFh 7E0000h to 7E7FFFh 7E8000h to 7EFFFFh 7F0000h to 7F7FFFh 7F8000h to 7F8FFFh 7F9000h to 7F9FFFh 7FA000h to 7FAFFFh 7FB000h to 7FBFFFh 7FC000h to 7FCFFFh 7FD000h to 7FDFFFh 7FE000h to 7FEFFFh 7FF000h to 7FFFFFh
Bank
Sector
Bank D
SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 SA256 SA257 SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
Bank Address CE0f CE1f A21 A20 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1
22
MB84VP24491HK-70
* Sector Group Address Table (128M Page Flash)
Sector Group CE0f CE1f SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 SGA17 SGA18 SGA19 SGA20 SGA21 SGA22 SGA23 SGA24 SGA25 SGA26 SGA27 SGA28 SGA29 SGA30 SGA31 SGA32 SGA33 SGA34 SGA35 SGA36 SGA37 SGA38 SGA39 SGA40 SGA41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A17 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA38 SA39 to SA42 SA43 to SA46 SA47 to SA50 SA51 to SA54 SA55 to SA58 SA59 to SA62 SA63 to SA66 SA67 to SA70 SA71 to SA74 SA75 to SA78 SA79 to SA82 SA83 to SA86 SA87 to SA90 SA91 to SA94 SA95 to SA98 SA99 to SA102 SA103 to SA106 SA107 to SA110 SA111 to SA114 SA115 to SA118 SA119 to SA122 SA123 to SA126 SA127 to SA130 SA131 to SA134
(Continued)
23
MB84VP24491HK-70
(Continued)
Sector Group CE0f CE1f SGA42 SGA43 SGA44 SGA45 SGA46 SGA47 SGA48 SGA49 SGA50 SGA51 SGA52 SGA53 SGA54 SGA55 SGA56 SGA57 SGA58 SGA59 SGA60 SGA61 SGA62 SGA63 SGA64 SGA65 SGA66 SGA67 SGA68 SGA69 SGA70 SGA71 SGA72 SGA73 SGA74 SGA75 SGA76 SGA77 SGA78 SGA79 SGA80 SGA81 SGA82 SGA83 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A20 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A19 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 A16 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 Sectors SA135 to SA138 SA139 to SA142 SA143 to SA146 SA147 to SA150 SA151 to SA154 SA155 to SA158 SA159 to SA162 SA163 to SA166 SA167 to SA170 SA171 to SA174 SA175 to SA178 SA179 to SA182 SA183 to SA186 SA187 to SA190 SA191 to SA194 SA195 to SA198 SA199 to SA202 SA203 to SA206 SA207 to SA210 SA211 to SA214 SA215 to SA218 SA219 to SA222 SA223 to SA226 SA227 to SA230 SA231 to SA234 SA235 to SA238 SA239 to SA242 SA243 to SA246 SA247 to SA250 SA251 to SA254 SA255 to SA258 SA259 SA260 SA261 SA262 SA263 SA264 SA265 SA266 SA267 SA268 SA269
24
MB84VP24491HK-70
* Sector Group Protection Verify Autoselect Codes (128M Page Flash) A7 A6 A5 A4 A3 A2 A1 A0 Type A22 to A12 Manufacture's Code Device Code Extended Device Code*2 BA BA BA Sector Group Addresses L L L L L L L L L L X X X X L X X X X L L L H H L L L H H L L L H H H L H L H L
Code (HEX) 04h 227Eh 2221h 2200h 01h*1
Sector Group Protection
Legend: L = VIL, H = VIH, X= VIL or VIH *1 : Sector Group can be protected by "Extended Sector Group Protection", and "New Sector Protection (PPB Protection)". Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : A read cycle at address (BA) 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended Device Codes, will be required. Therefore the system may continue reading out these Extended Device Codes at the address of (BA) 0Eh, as well as at (BA) 0Fh.
25
MB84VP24491HK-70
* Command Definitions (128M Page Flash)
Command Sequence Read/Reset Read/Reset Autoselect Program Chip Erase Sector Erase Program/Erase Suspend Program/Erase Resume Set to Fast Mode Fast Program Reset from Fast Mode *1 Extended Sector Group Protection *2 Query HiddenROM Entry HiddenROM Program *3 HiddenROM Exit *3 HiddenROM Protect *3 Password Program Password Unlock Password Verify Password Mode Locking Bit Program Persistent Protection Mode Locking Bit Program PPB Program PPB Verify All PPB Erase PPB Lock Bit Set PPB Lock Bit Verify DPB Write DPB Erase DPB Verify Bus Write Cycles Req'd 1 3 3 4 6 6 1 1 3 2 2 4 1 3 4 4 6 First Bus Write Cycle Addr. XXXh 555h 555h 555h 555h 555h BA BA 555h XXXh BA XXXh (BA) 55h 555h 555h 555h 555h 555h 555h 555h 555h 555h 555h 555h Data F0h AAh AAh AAh AAh AAh B0h 30h AAh A0h 90h 60h 98h AAh AAh AAh AAh AAh AAh AAh AAh AAh AAh AAh Second Bus Write Cycle Addr. RA 2AAh 2AAh 2AAh 2AAh 2AAh -- -- 2AAh PA XXXh SGA+ WPH -- 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh Data RD 55h 55h 55h 55h 55h -- -- 55h PD *4 F0h 60h -- 55h 55h 55h 55h 55h 55h 55h 55h 55h 55h 55h Third Bus Write Cycle Addr. -- 555h (BA) 555h 555h 555h 555h -- -- 555h -- -- SGA+ WPH -- 555h 555h
(HRBA)
Fourth Bus Read/Write Cycle Addr. -- RA -- PA 555h 555h -- -- -- -- -- SGA+ WPH -- -- (HRA) PA XXXh OPBP XX0h XX1h XX2h XX3h XX0h PWA PL Data -- RD -- PD AAh AAh -- -- -- -- -- SD -- -- PD 00h 68h PD0 PD1 PD2 PD3 PD0 PWD 68h
Fifth Bus Write Cycle Addr. -- -- -- -- 2AAh 2AAh -- -- -- -- -- -- -- -- -- -- OPBP Data -- -- -- -- 55h 55h -- -- -- -- -- -- -- -- -- -- 48h
Sixth Bus Write Cycle Addr. -- -- -- -- 555h SA -- -- -- -- -- -- -- -- -- -- Data -- -- -- -- 10h 30h -- -- -- -- -- -- -- -- -- --
Seventh Bus Write Cycle Addr. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Data -- F0h 90h A0h 80h 80h -- -- 20h -- -- 40h -- 88h A0h 90h 60h 38h 38h 38h 38h 28h C8h 60h
555h 555h 555h 555h 555h 555h 555h 555h 555h
OPBP RD(0)
4
--
--
--
--
--
--
7 4 6
XX1h -- PL
PD1 -- 48h
XX2h -- XXXh
PD2 -- RD(0)
XX3h -- --
PD3 -- --
6 6 4 4 3 4 4 4 4
555h 555h 555h 555h 555h 555h 555h 555h 555h
AAh AAh AAh AAh AAh AAh AAh AAh AAh
2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh 2AAh
55h 55h 55h 55h 55h 55h 55h 55h 55h
555h 555h (BA) 555h 555h 555h (BA) 555h 555h 555h (BA) 555h
60h 60h 90h 60h 78h 58h 48h 48h 58h
SPML SGA+WP SGA+WP WP -- SA SA SA SA
68h 68h RD(0) 60h -- RD(1) X1h X0h RD(0)
SPML SGA+WP -- SGA+WP -- -- -- -- --
48h 48h -- 40h -- -- -- -- --
XXXh XXXh -- XXXh -- -- -- -- --
RD(0) RD(0) -- RD(0) -- -- -- -- --
-- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
(Continued)
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MB84VP24491HK-70
(Continued)
Legend: RA = Address of the memory location to be read PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A22, A21, A20, A19, A18, A17, A16, A15, A14, A13 and A12 will uniquely select any sector. BA = Bank Address. Address settled by A22, A21, A20, A19 will select Bank A, Bank B, Bank C and Bank D. RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SGA = Sector group address to be protected. WPH = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0) SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the HiddenROM area Word Mode : 000000h to 00007Fh HRBA = Bank Address of the HiddenROM area (A22 = A21 = A20 = VIL) RD (0) = Read Data bit. If protected, DQ0 = 1, if unprotected, DQ0 = 0 RD (1) = Read Data bit. If protected, DQ1 = 1, if unprotected, DQ1 = 0 OPBP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 1, 0, 1, 0) PWA/PWD = Password Address/Password Data PL = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 1, 0, 1, 0) SPML = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 1, 0, 0, 1, 0) WP = (A7, A6, A5, A4, A3, A2, A1, A0) is (0, 0, 0, 0, 0, 0, 1, 0) *1: This command is valid during Fast Mode. *2: This command is valid while RESET = VID. *3: This command is valid during HiddenROM mode. *4: The data "00h" is also acceptable. Notes : * Address bits A22 to A11 = X = "H" or "L" for all address commands except for PA, SA, BA, SGA, OPBP PWA, PL, SPML, WP WPH. , , * Bus operations are defined in this document. * The system should generate the following address patterns: Word Mode : 555h or 2AAh to addresses A10 to A0 * Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
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MB84VP24491HK-70
3. AC Characteristics
* Read Only Operations Characteristics (Flash) (128M Page Flash) Symbol Parameter JEDEC Read Cycle Time Address to Output Delay Page Read Cycle Time Page Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Address, CEf or OE, Whichever Occurs First tAVAV tAVQV -- -- tELQV tGLQV tEHQZ tGHQZ tAXQX Standard tRC tACC tPRC tPACC tCE tOE tDF tDF tOH Test Setup -- CEf = VIL OE = VIL -- CEf = VIL OE = VIL OE = VIL -- -- -- -- Value* Unit Min 70 20 5 Max 70 20 70 20 20 20 ns ns ns ns ns ns ns ns ns
* : Test Conditions- Output Load : 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCf Timing measurement reference level Input: 0.5xVCCf Output: 0.5xVCCf
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MB84VP24491HK-70
* Write/Erase/Program Operations (Flash) (128M Page Flash) Parameter Write Cycle Time Address Setup Time Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Setup Time Read Output Enable Hold Time Toggle and Data Polling Read Recover Time Before Write Read Recover Time Before Write (OE High to CEf Low) CEf Setup Time WE Setup Time CEf Hold Time WE Hold Time Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Programming Operation Sector Erase Operation *2 VCCf Setup Time Rise Time to VID *3 Rise Time to VACC *4 Voltage Transition Time *3 Write Pulse Width*3 Recover Time from RY/BY RESET Pulse Width RESET High Level Period Before Read Program/Erase Valid to RY/BY Delay Delay Time from Embedded Output Enable Erase Time-out Time Erase Suspend Transition Time Symbol JEDEC Standard tAVAV tWC tAS tAVWL -- tWLAX -- tDVWH tWHDX -- -- tGHWL tGHEL tELWL tWLEL tWHEH tEHWH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- -- -- -- -- tASO tAH tAHT tDS tDH tOES tOEH tGHWL tGHEL tCS tWS tCH tWH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVACCR tVLHT tWPP tRB tRP tRH tBUSY tEOE tTOW tSPD Value*1 Typ 6 0.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns s s ns ns ns ns ns s s
Min 70 0 15 35 0 30 0 0 0 10 0 0 0 0 0 0 40 40 25 25 50 500 500 4 100 0 500 50 50
Max 90 70 20
*1 : Test Conditions- Output Load : 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCf Timing measurement reference level Input: 0.5xVCCf Output: 0.5xVCCf *2 : This does not include the preprogramming time. *3 : This timing is for Sector Group Protection / Unprotection. *4 : This timing is for Accelerated Program operation. 29
MB84VP24491HK-70
* Read Operation Timing Diagram (128M Page Flash)
tRC
Address
Address Stable
tACC
CEf
tOE tDF
OE
tOEH
WE
tCE tOH
Outputs
High-Z
Output Valid
High-Z
CEf : CE0f or CE1f
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MB84VP24491HK-70
* Page Read Operation Timing Diagram (128M Page Flash)
A22 to A2 A2 to A0
Same page Addresses
Aa tRC tACC tCE
Ab tPRC
Ac tPRC
Ad
CEf
tOEH
OE WE
tOE tDF tPACC tOH tPACC tOH Db tPACC tOH Dc tOH Dd
Output
High-Z
Da
CEf : CE0f or CE1f
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MB84VP24491HK-70
* Hardware Reset/Read Operation Timing Diagram (128M Page Flash)
tRC
Address
tACC
Address Stable
CEf
tRH
tRP
tRH
tCE
RESET
tOH High-Z
Outputs
Outputs Valid
CEf : CE0f or CE1f
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MB84VP24491HK-70
* Alternate WE Controlled Program Operation Timing Diagram (128M Page Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA tRC
Address
555h tWC
CEf
tCS tCH tCE
OE
tGHWL tWP tWPH tOE tWHWH1
WE
tDS tDH tDF tOH
Data
A0h
PD
DQ7
DOUT
DOUT
CEf : CE0f or CE1f Notes : * * * * *
PA is address of the memory location to be programmed. PD is data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence.
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MB84VP24491HK-70
* Alternate CEf Controlled Program Operation Timing Diagram (128M Page Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH PD DQ7 DOUT
Data
A0h
CEf : CE0f or CE1f Notes : * * * * * PA is address of the memory location to be programmed. PD is data to be programmed at word address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence.
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MB84VP24491HK-70
* Chip/Sector Erase Operation Timing Diagram (128M Page Flash)
Address
555h tWC 2AAh tAS tAH 555h 555h 2AAh SA*
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS AAh tDH 55h 80h AAh 55h
30h for Sector Erase
10h/30h
Data
tVCS
VCCf
CEf : CE0f or CE1f
* : SA is the sector address for Sector Erase. Addresses = 555h (Word) for Chip Erase.
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MB84VP24491HK-70
* Data Polling during Embedded Algorithm Operation Timing Diagram (128M Page Flash)
CEf
tCH
tOE
tDF
OE
tOEH
WE
tCE * DQ7 = Valid Data
DQ7
Data
DQ7
High-Z
tWHWH1 or 2
DQ6 to DQ0
Data tBUSY
DQ6 to DQ0 = Output Flag tEOE
DQ6 to DQ0 Valid Data
High-Z
RY/BY
CEf : CE0f or CE1f * : DQ7 = Valid Data (The device has completed the Embedded operation) .
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MB84VP24491HK-70
* AC Waveforms for Toggle Bit I during Embedded Algorithm Operations (128M Page Flash)
Address
tAHT tASO tAHT tAS
CEf
tCEPH
WE
tOEH
tOEPH tOEH
OE
tDH tOE tCE
DQ 6/DQ2
Data
tBUSY
Toggle Data
Toggle Data
Toggle Data
*
Stop
Toggling
Output Valid
RY/BY
CEf : CE0f or CE1f * : DQ6 stops toggling (The device has completed the Embedded operation).
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MB84VP24491HK-70
* Bank-to-Bank Read/Write Timing Diagram (128M Page Flash)
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
Address
BA1
tAS
BA2 (555h)
tAH
BA1
tACC tCE
BA2 (PA)
BA1
tAS tAHT
BA2 (PA)
CEf
tOE tCEPH
OE
tGHWL tWP tOEH tDF
WE
tDS tDH tDF
DQ
Valid Output
Valid Intput (A0h)
Valid Output
Valid Intput (PD)
Valid Output
Status
CEf : CE0f or CE1f Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1 : Address corresponding to Bank 1 BA2 : Address corresponding to Bank 2
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MB84VP24491HK-70
* RY/BY Timing Diagram during Program/Erase Operation Timing Diagram (128M Page Flash)
CEf
Rising edge of the last WE signal
WE
Entire programming or erase operations
RY/BY
tBUSY
CEf : CE0f or CE1f
* RESET, RY/BY Timing Diagram (128M Page Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
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MB84VP24491HK-70
* Temporary Sector Group Unprotection Timing Diagram (128M Page Flash)
VCCf
tVCS
tVIDR tVLHT
VID VIH RESET
CEf
WE
tVLHT Program or Erase Command Sequence tVLHT
RY/BY
Unprotection period
CEf : CE0f or CE1f
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MB84VP24491HK-70
* Extended Sector Group Protection Timing Diagram (128M Page Flash)
VCCf
tVCS
RESET
tVIDR
tVLHT tWC tWC SGAX SGAX SGAY
Address
A7, A6, A5 A4, A3, A2 A0
A1
CEf
OE
tWP
TIME-OUT
WE Data
60h 60h 40h tOE 01h 60h
CEf : CE0f or CE1f
SGAX : Sector Group Address to be protected SGAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 s (Min)
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MB84VP24491HK-70
* Accelerated Program Timing Diagram (128M Page Flash)
VCCf
tVCS
tVACCR tVLHT
VACC VIH WP/ACC
CEf
WE
tVLHT Program Sequence tVLHT
RY/BY
Acceleration period
CEf : CE0f or CE1f
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MB84VP24491HK-70
4. Erase and Programing Performance (128M Page Flash)
Value Parameter Min Sector Erase Time Word Programming Time Chip Programming Time Erase/Program Cycle -- -- -- 100,000 Typ 0.5 6.0 50.3 -- Max 2 100 200 -- s s s cycle Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead -- Unit Comments
Note: Typical Erase conditions TA = + 25C, VCC = 2.9 V Typical Program conditions TA = + 25C, VCC = 2.9 V, Data = checker
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MB84VP24491HK-70
s 32 M FCRAM CHARACTERISTICS for MCP
1. Power Down (32M Page Mode FCRAM)
* Power Down (32M Page mode FCRAM) The Power Down is to enter low power idle state when CE2r stays Low. The 32M page mode FCRAM has four power down mode, Sleep, 4M Partial, 8M Partial, and 16M Partial. These can be programmed by series of read/write operation. Each mode has follwoing features. Mode Sleep (default) 4M Partial 8M Partial 16M Partial Data Retention No 4M bit 8M bit 16M bit Retention Address N/A 00000h to 3FFFFh 00000h to 7FFFFh 00000h to FFFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2r is brought to Low for Power Down. It is not required to program to Sleep mode after power-up. * Power Down Program Sequence (32M Page mode FCRAM) The program requires total 6 read/write operation with unique address and data. Between each read/write operation requires that device be in standby mode. Following table shows the detail sequence. Cycle # 1st 2nd 3rd 4th 5th 6th Operation Read Write Write Write Write Read Address 1FFFFFh (MSB) 1FFFFFh 1FFFFFh 1FFFFFh 1FFFFFh Address Key Data Read Data (RDa) RDa RDa 0000h Data Key Read Data (RDb)
The first cycle is to read from most significient address (MSB). The second and third cycle are to write back the data (RDa) read by first cycle. If the third cycle is written into the different address, the program is cancelled and the data written by the second or third cycle is valid as a normal write operation. The forth and fifth cycle is to write the data key for program. The data of forth cycle must be all 0's and data of fifth cycle is a data key for mode selection. If the forth cycle is written into different address, the program is also cancelled. The last cycle is to read from specific address key for mode selection. The both data key written by fifth cycle and address key must be the same mode for proper programming. Once this program sequence is performed from a Partial mode to other Partial mode, the write data may be lost. So, it should perform this program prior to regular read/write operation if Partial mode is used.
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MB84VP24491HK-70
* Address Key (32M Page mode FCRAM) The address key has following format. Address A20 1 0 1 0 A19 1 1 0 0 A18 to A0 1 1 1 1 Binary 1FFFFFh 0FFFFFh 17FFFFh 07FFFFh
Mode Sleep (default) 4M Partial 8M Partial 16M Partial * Data Key (32M Page mode FCRAM) The data key has following format.
Mode Sleep (default) 4M Partial 8M Partial 16M Partial
Data DQ15 to DQ8 0 0 0 0 DQ7 to DQ2 0 0 0 0 DQ1 1 1 0 0 DQ0 1 0 1 0
The upper byte of data code may be ignored and it is just for recommendation to write 0's to upper byte for future compatibility.
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MB84VP24491HK-70
2. AC Characteristics
* READ OPERATION (32M Page mode FCRAM) Value Parameter Read Cycle Time CE1r Access Time OE Access Time Address Access Time LB / UB Access Time Page Address Access Time Page Read Cycle Time Output Data Hold Time CE1r Low to Output Low-Z OE Low to Output Low-Z LB / UB Low to Output Low-Z CE1r High to Output High-Z OE High to Output High-Z LB / UB High to Output High-Z Address Setup Time to CE1r Low Address Setup Time to OE Low Address Invalid Time Page Address Invalid Time Address Hold Time from CE1r High Address Hold Time from OE High CE1r High Pulse Width Symbol Min tRC tCE tOE tAA tBA tPAA tPRC tOH tCLZ tOLZ tBLZ tCHZ tOHZ tBHZ tASC tASO tAX tAXP tCHAH tOHAH tCP 70 -- -- -- -- -- 25 5 3 0 0 -- -- -- -5 10 -- -- -5 -5 15 Max 1000 70 40 70 30 18 1000 -- -- -- -- 20 20 20 -- -- 10 10 -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *5, *8 *6, *8 *9 *1, *2 *3 *3 *3, *5 *3 *3, *6 *1, *6, *7 *3 *4 *4 *4 *4 *4 *4 Unit Remarks
*1 : Maximum value is applicable if CE1r is kept at Low without change of address input of A20 to A3. If needed by system operation, please contact local FUJITSU representative for the relaxation of 1 s limitation. *2 : Address should not be changed within minimum tRC. *3 : The output load 30 pF. *4 : The output load 5 pF without any other load. *5 : Applicable to A20 to A3 when CE1r is kept at Low. *6 : Applicable only to A2, A1 and A0 when CE1r is kept at Low for the page address access. *7 : In case Page Read Cycle is continued with keeping CE1r stays Low, CE1r must be brought to High within 4 s. In other words, Page Read Cycle must be closed within 4 s. *8 : Applicable when at least two of address inputs among applicable are switched from previous state. *9 : tRC(Min) and tPRC(Min) must be satisfied.
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MB84VP24491HK-70
* WRITE OPERATION (32M Page mode FCRAM) Value Parameter Write Cycle Time Address Setup Time CE1r Write Pulse Width WE Write Pulse Width LB / UB Write Pulse Width CE1r Write Recovery Time WE Write Recovery Time LB / UB Write Recovery Time Data Setup Time Data Hold Time Address Invalid Time after Write OE High to CE1r Low Setup Time for Write OE High to Address Setup Time for Write LB and UB Write Pulse Overlap CE1r High Pulse Width Symbol Min tWC tAS tCW tWP tBW tWRC tWR tBR tDS tDH tAXW tOHCL tOES tBWO tCP 70 0 45 45 45 15 15 15 20 0 -- -5 0 20 15 Max 1000 -- -- -- -- -- 1000 1000 -- -- 10 -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns *5 *6 *7 *1, *2 *2 *3 *3 *3 *4 *4 *4 Unit Remarks
*1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by system operation, please contact local FUJITSU representative for the relaxation of 1 s limitation. *2 : Minimum value must be equal or greater than the sum of write pulse (tCW, tWP or tBW) and write recovery time (tWRC, tWR or tBR). *3 : Write pulse is defined from High to Low transition of CE1r, WE, or LB / UB, whichever occurs last. *4 : Write recovery is defined from Low to High transition of CE1r, WE, or LB / UB, whichever occurs first. *5 : Applicable to any address change when CE1r stays Low. *6 : If OE is Low after minimum tOHCL, read cycle is initiated. In other word, OE must be brought to High within 5ns after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum tRC is met. *7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the same time or before new address valid. Once read cycle is initiated, new write pulse should be input after minimum tRC is met.
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MB84VP24491HK-70
* POWER DOWN PARAMETERS (32M Page mode FCRAM) Value Parameter CE2r Low Setup Time for Power Down Entry CE2r Low Hold Time after Power Down Entry CE1r High Hold Time following CE2r High after Power Down Exit [SLEEP mode only] CE1r High Hold Time following CE2r High after Power Down Exit [not in SLEEP mode] CE1r High Setup Time following CE2r High after Power Down Exit *1 : Applicable also to power-up. *2 : Applicable when 4M, 8M, and 16M Partial mode is programmed. * OTHER TIMING PARAMETERS (32M Page mode FCRAM) Value Parameter CE1r High to OE Invalid Time for Standby Entry CE1r High to WE Invalid Time for Standby Entry CE1r High Hold Time following CE2r High after Power-up Input Transition Time Symbol Min tCHOX tCHWX tCHH tT 10 10 300 1 Max -- -- -- 25 ns ns s ns *2 *1 Unit Remarks Symbol Min tCSP tC2LP tCHH tCHHP tCHS 10 70 300 1 0 Max -- -- -- -- -- ns ns s s ns *1 *2 Unit Remarks
*1 : Some data might be written into any address location if tCHWX(Min) is not satisfied. *2 : The Input Transition Time (tT) at AC testing is 5 ns as shown in below. If actual tT is longer than 5ns, it may violate AC specification of some timing parameters. * AC TEST CONDITIONS (32M Page mode FCRAM) Description Input High Level Input Low Level Input Timing Measurement Level Input Transition Time Symbol VIH VIL VREF tT Test Setup -- -- -- Between VIL and VIH Value VCCr VSS VCCr x 0.5 5 Unit V V V ns Remarks
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MB84VP24491HK-70
* READ Timing #1 (Basic Timing) (32M Page FCRAM)
tRC Address tASC CE1r tOE OE tOHZ tBA LB / UB tBLZ tOLZ DQ (Output) tCLZ tOH tBHZ tCE Address Valid tCHAH tASC
tCP tCHZ
Valid Data Output
Note : CE2r and WE must be High for entire read cycle.
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MB84VP24491HK-70
* READ Timing #2 (OE & Address Access) (32M Page FCRAM)
tAx
tRC Address Address Valid tAA CE1r
tRC Address Valid tAA tOHAH
Low
tASO OE
tOE
LB / UB tOHZ tOLZ DQ (Output) Valid Data Output Valid Data Output tOH tOH
Note : CE2r and WE must be High for entire read cycle.
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MB84VP24491HK-70
* READ Timing #3 (LB / UB Byte Access) (32M Page FCRAM)
tAX Address tAA CE1r, OE
tRC Address Valid
tAx
Low tBA
tBA LB tBA UB tBHZ tBLZ DQ7 to DA0 (Output) Valid Data Output DQ15 to DQ8 (Output) tOH
tBHZ tBLZ tOH
Valid Data Output tBLZ
tBHZ tOH
Valid Data Output
Note : CE2r and WE must be High for entire read cycle.
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MB84VP24491HK-70
* READ Timing #4 (Page Address Access after CE1r Control Access) (32M Page FCRAM)
tRC Address (A20 to A3) tRC Address (A2 to A0) tASC CE1r tCE tCHZ Address Valid Address Valid tPRC
Address Valid
tPRC
Address Valid
tPRC
Address Valid
tPAA
tPAA
tPAA
tCHAH
OE
LB / UB tCLZ DQ (Output) Valid Data Output (Normal Access) Valid Data Output (Page Access) tOH tOH tOH tOH
Note : CE2r and WE must be High for entire read cycle.
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MB84VP24491HK-70
* READ Timing #5 (Random and Page Address Access) (32M Page FCRAM)
tRC Address (A20 to A3) tRC Address (A2 to A0)
Address Valid
tAX
tRC Address Valid
tAx
Address Valid tPRC
Address Valid
tRC
Address Valid
tPRC
Address Valid
tAA CE1r
tPAA
tAA
tPAA
Low tASO tOE
OE tBA LB / UB tOLZ tBLZ tOH tOH tOH tOH
DQ (Output)
Valid Data Output (Normal Access)
Valid Data Output (Page Access)
Note : CE2r and WE must be High for entire read cycle. Either or both LB and UB must be Low when both CE1r and OE are Low.
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MB84VP24491HK-70
* WRITE Timing #1 (Basic Timing) (32M Page FCRAM)
tWC Address tAS CE1r tAS WE tAS LB, UB tOHCL OE tDS DQ (Input) Valid Data Input tDH tBR tAS tWR tAS Address Valid tWRC tAS
tCW
tWP
tBW
Note : CE2r must be High for write cycle.
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MB84VP24491HK-70
* WRITE Timing #2 (WE Control) (32M Page FCRAM)
tWC Address Address Valid tWC Address Valid
tOHAH CE1r Low tAS WE tWP tWR tAS tWP tWR
LB, UB tOES OE tOHZ DQ (Input) Valid Data Input Valid Data Input tDS tDH tDS tDH
Note : CE2r must be High for write cycle.
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MB84VP24491HK-70
* WRITE Timing #3-1 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC Address Address Valid tWC Address Valid
CE1r
Low tAS tWP tAS tWP
WE tBR LB tBR UB tDS DQ7 to DQ0 (Input) Valid Data Input DQ15 to DQ8 (Input) Valid Data Input tDS tDH tDH
Note : CE2r must be High for write cycle.
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MB84VP24491HK-70
* WRITE Timing #3-2 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC Address Address Valid tWC Address Valid
CE1r
Low tWR tWR
WE tAS LB tAS UB tDS DQ7 to DQ0 (Input) Valid Data Input DQ15 to DQ8 (Input) Valid Data Input tDS tDH tDH tBW tBW
Note : CE2r must be High for write cycle.
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MB84VP24491HK-70
* WRITE Timing #3-3 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC Address Address Valid tWC Address Valid
CE1r
Low
WE tAS LB tAS UB tDS DQ7 to DQ0 (Input) Valid Data Input DQ15 to DQ8 (Input) Valid Data Input tDS tDH tDH tBW tBR tBW tBR
Note : CE2r must be High for write cycle.
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MB84VP24491HK-70
* WRITE Timing #3-4 (WE / LB / UB Byte Write Control) (32M Page FCRAM)
tWC Address Address Valid tWC Address Valid
CE1r
Low
WE tAS LB tBWO tDS DQ7 to DQ0 (Input) tAS UB tDS DQ15 to DQ8 (Input)
Valid Data Input Valid Data Input
tBW
tBR
tAS
tBW
tBR
tDH
tDS
Valid Data Input
tDH
tBW
tBR
tAS
tBWO tBW
tBR
tDH
tDS
Valid Data Input
tDH
Note : CE2r must be High for write cycle.
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MB84VP24491HK-70
* READ / WRITE Timing #1-1 (CE1r Control) (32M Page FCRAM)
tWC Address tCHAH CE1r tCP tCP tAS Write Address tWRC tCW tASC tRC Read Address tCHAH
tCE
WE
UB, LB tOHCL OE tCHZ tOH DQ Read Data Output Write Data Input tDS tDH tCLZ tOH
Note : Write address is valid from either CE1r or WE of last falling edge.
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MB84VP24491HK-70
* READ / WRITE Timing #1-2 (CE1r / WE / OE Control) (32M Page FCRAM)
tWC Address tCHAH CE1r tCP tWP WE tCP tAS Write Address tWR tASC tRC Read Address tCHAH
tCE
UB, LB tOHCL OE tCHZ tOH DQ Read Data Output Write Data Input Read Data Output tDS tDH tOLZ tOH
tOE
Note : OE can be Low fixed in write operation under CE1r control RD-WR-RD operation.
61
MB84VP24491HK-70
* READ / WRITE Timing #2 (OE, WE Control) (32M Page FCRAM)
tWC Address Write Address tRC Read Address tAA tOHAH CE1r Low tAS WE tOES tWP tWR tOHAH
UB, LB
tASO OE tOHZ tOH DQ Read Data Output Write Data Input tDS tDH tOLZ
tOE
tOHZ tOH
Read Data Output
Note : CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE.
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MB84VP24491HK-70
* READ / WRITE Timing #3 (OE, WE, LB, UB Control) (32M Page FCRAM)
tWC Address Write Address tRC Read Address tAA tOHAH CE1r Low tOHAH
WE tOES UB, LB tBHZ OE tBHZ tOH DQ Read Data Output Write Data Input Read Data Output tDS tDH tBLZ tOH tASO tAS tBW tBR
tBA
Note : CE1r can be tied to Low for WE and OE controlled operation. When CE1r is tied to Low, output is exclusively controlled by OE.
63
MB84VP24491HK-70
* POWER-UP Timing (32M Page FCRAM)
CE1r tCHH CE2r
VCCr
0V
VCCr Min
Note : The tCHH specifies after VCCr reaches specified minimum level and applicable both CE1r and CE2r. * POWER DOWN Entry and Exit Timing
CE1r tCHS CE2r tCSP DQ Power Down Entry tC2LP High-Z Power Down Mode Power Down Exit tCHH (tCHHP)
Note : This Power Down mode can be also used as a reset timing if POWER-UP timing above could not be satisfied and Power-Down program was not performed prior to this reset. * Standby Entry Timing after Read or Write (32M Page FCRAM)
CE1r tCHOX OE tCHWX
WE Active (Read) Standby Active (Write) Standby
Note : Both tCHOX and tCHWX define the earliest entry timing for Standby mode. If either of timing is not satisfied, it takes tRC (Min) period for Standby mode from CE1r Low to High transition.
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MB84VP24491HK-70
* POWER DOWN PROGRAM Timing (32M Page FCRAM)
tRC Address MSB*1
tWC MSB*1
tWC MSB*1
tWC MSB*1
tWC MSB*1
tRC Key*2
tCP CE1r
tCP
tCP
tCP
tCP
tCP*4
OE
WE
LB, UB
DQ*3
RDa Cycle #1
RDa Cycle #2
RDa Cycle #3
00 Cycle #4
Key*3 Cycle #5
RDb Cycle #6
*1 : The all address inputs must be High from Cycle #1 to #5. *2 : The address key must confirm the format specified in "s 32 M FCRAM CHARACTERISTICS for MCP 1. Power Down Program Timing (32 M Page FCRAM) ". If not, the operation and data are not guaranteed. *3 : The data key must confirm the format specified in "s 32 M FCRAM CHARACTERISTICS for MCP 1. Power Down Program Timing (32 M Page FCRAM) ". If not, the operation and data are not guaranteed. *4 : After tCP following Cycle #6, the Power Down Program is completed and returned to the normal operation.
65
MB84VP24491HK-70
s PIN CAPACITANCE
Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Condition VIN = 0 VOUT = 0 VIN = 0 VIN = 0 Value Min Typ 11.0 12.0 14.0 21.5 Max 14.0 16.0 16.0 26.0 Unit pF pF pF pF
Note: Test conditions TA = + 25C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
s CAUTION
* The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET. * Without the high voltage (VID) , sector group protection can be achieved by using "Extended Sector Group Protection" command.
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MB84VP24491HK-70
s ORDERING INFORMATION
MB84VP24491 HK -70 PBS
Package Type PBS = 73-ball FBGA Speed Option
Device Revision
Device Number/Description 128Mega-bit (4M x 16-bit + 4M x 16-bit) Dual Operation Flash Memory Dual Chip Enable 3.0V-only Read, Program, and Erase 32Mega-bit(2M x 16-bit) Mobile FCRAM
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MB84VP24491HK-70
s PACKAGE DIMENSION
73-ball plastic FBGA (BGA-73P-M03)
11.600.10(.457.004) 0.20(.008) S B B 1.19 -0.10 .047 -.004 (Seated height)
+0.15 +.006
0.40(.016) REF
0.80(.031) REF 10
0.80(.031) REF A 8.000.10 (.315.004)
9 8 7 6
0.40(.016) REF 0.10(.004) S
5 4 3 2 1
INDEX-MARK AREA
0.390.10 (Stand off) (.015.004) S 0.20(.008) S A
M
L
K
J
H
G
F
E
D
C
B
A
INDEX BALL 73-o0.45 73-o0.18
+0.10 -.005 +.004 -.002
o0.08(.003)
M
S AB
0.10(.004) S
C
2003 FUJITSU LIMITED B73003S-c-1-1
Dimensions in mm (inches) . Note : The values in parentheses are reference values.
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MB84VP24491HK-70
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0312 (c) FUJITSU LIMITED Printed in Japan

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